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| IMAGE SENSOR Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 Operating the back-thinned CCD in TDI mode delivers high sensitivity. TDI-CCD captures clear and bright images even under low-light-level conditions. During TDI mode, the CCD captures an image of a moving object while transferring integrated signal charges synchronously with the object movement. This operation mode dramatically boosts sensitivity to high levels even when capturing fast moving objects. Our new TDI-CCD uses the back-thinned structure to achieve even higher quantum efficiency over a wide spectral range from UV to near IR region (200 to 1100 nm). Features Applications l TDI mode gives high sensitivity l High-speed, continuous image acquisition l Back-thinned structure ensures high sensitivity from UV to near IR l Multiple ports for high-speed line rate l Sequential imaging of high-speed moving samples l Inspection tasks on electronic parts production line l Semiconductor inspection l Flow cytometery TDI (Time Delay Integration) mode In FFT-CCD, signal charges in each line are vertically transferred during charge readout. TDI mode synchronizes this vertical transfer timing with the movement of the object, so that signal charges are integrated a number of times equal to the number of vertical stages of the CCD pixels. In the TDI mode, the signal charges must be transferred in the same direction at the same speed as those of the object to be imaged. These speeds are expressed by the following equation: v=fxd v: Object moving speed, Charge transfer speed, f: Vertical transfer frequency, d: Pixel size In the right figure, when the first stage charges are transferred to the second stage, an additional charges are produced in the second stage by photoelectric conversion and accumulated. When this operation is continuously repeated until reaching the last stage M (the number of vertical stages), signal charges which are M times greater than the initial charges are accumulated. Since the signal charges on each line are output from the CCD horizontal shift register, a two-dimensional image can be continuously acquired. In this way the TDI mode achieves sensitivity which is M times higher than linear image sensors (S/N is improved M times). The TDI mode also improves sensitivity variations compared to frame mode operation. s Selection guide Type No. S10200-02 S10201-04 S10202-08 S10202-16 Pixel size (m) Number of total pixels (H) x (V) 1040 x 128 2080 x 128 4160 x 128 4224 x 128 Number of active pixels (H) x (V) 1024 x 128 2048 x 128 4096 x 128 4096 x 128 q Schematic diagram showing integrated exposure by TDI mode CHARGE TRANSFER * OBJECT MOVEMENT Time1 Time2 Time3 FIRST STAGE * * * * * LAST STAGE M CHARGE KMPDC0139EA Number of ports 2 4 8 16 Pixel rate (MHz/port) Line rate (kHz) 50 100 Vertical transfer 12 x 12 30 Bidirectional s Specifications Parameter TDI stage Anti-blooming Vertical clock Horizontal clock Output circuit Package Window PRELIMINARY DATA Jan. 2007 Specification 128 FW x 100 (Min.) 3 phases 2 phases Two-stage MOSFET source follower Ceramic DIP Quarts glass 1 Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 s Spectral response (without window) 3000 (Typ. Ta=25 C) 100 90 (Typ. Ta=25 C) BACK-THINNED CCD S10200-02 S10201-04 S10202-08 S10202-16 PHOTO SENSITIVITY (V/J * cm2) QUANTUM EFFICIENCY (%) 2500 80 70 60 50 40 30 20 10 2000 1500 1000 500 0 200 300 400 500 600 700 800 900 1000 1100 FRONT-ILLUMINATED CCD 0 200 300 400 500 600 700 800 900 1000 1100 1200 WAVELENGTH (nm) KMPDB0268EA WAVELENGTH (nm) KMPDB0269EA s Sensor structure S10200-02 B PORT SIDE OSb1 OSb2 OFD OFG DGND 512 pixels TGb P3V P2V P1V TGa 128 pixels BIDIRECTIONAL TRANSFER OSa1 RG RD OD AGND OG SG P2H P1H A PORT SIDE KMPDC0251EA OSa2 S10201-04 B PORT SIDE OSb1 OSb2 OSb3 OSb4 OFD OFG DGND 512 pixels TGb P3V P2V P1V TGa 128 pixels BIDIRECTIONAL TRANSFER OSa1 RG RD OD AGND OG SG P2H P1H OSa2 OSa3 A PORT SIDE KMPDC0260EA 2 OSa4 Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 S10202-08 B PORT SIDE OSb3 OSb4 OSb5 OSb1 OSb2 OSb8 OFD OFG DGND 512 pixels TGb P3V P2V P1V TGa 128 pixels BIDIRECTIONAL TRANSFER OSa1 RG RD OD AGND OG SG P2H P1H OSa2 OSa3 OSa4 OSa5 A PORT SIDE OSa8 KMPDC0261EA S10202-16 B PORT SIDE OSb15 OSb1 OSb2 OSb16 OSb3 OSb4 OSb5 OSb6 OSb7 OSb8 OSb9 OFD OFG DGND 256 pixels TGb P3V P2V P1V TGa 128 pixels BIDIRECTIONAL TRANSFER RG RD OD AGND OG SG P2H P1H OSa15 A PORT SIDE OSa16 OSa1 OSa2 OSa3 OSa4 OSa5 OSa6 OSa7 OSa8 OSa9 KMPDC0262EA s Absolute maximum ratings (Ta=25 C) Parameter Operating temperature Storage temperature Output transistor drain voltage Reset drain voltage Overflow drain voltage Overflow gate voltage Summing gate voltage Output gate voltage Reset gate voltage Transfer gate voltage Vertical clock voltage Horizontal clock voltage Symbol Topr Tstg VOD VRD VOFD VOFG VSG VOG VRG VTG VP1V, VP2V, VP3V VP1H, VP2H Min. -50 -50 -0.5 -0.5 -0.5 -10 -10 -10 -10 -10 -10 -10 Typ. Max. 60 70 25 18 18 15 15 15 15 15 15 15 Unit C C V V V V V V V V V V 3 Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 Symbol VOD VRD VOG VDGND, VAGND VOFD VOFG VP1VH, VP2VH, VP3VH VP1VL, VP2VL, VP3VL VP1HH, VP2HH VP1HL, VP2HL VSGH VSHL VRGH VRGL VTGH VTGL Min. 12 11 3 4 0 4 -6 4 -6 4 -6 7 -6 4 -6 Typ. 15 12 5 0 6 4 6 -5 6 -5 6 -5 8 0 6 -5 Max. 18 13 7 9 6 8 -4 8 -4 8 -4 9 8 -4 Unit V V V V V V V V V V V s Operating conditions (TDI m ode, Ta=25 C) Parameter Output transistor drain voltage Reset drain voltage Output gate voltage Substrate voltage Overflow drain voltage Overflow gate voltage Vertical shift register clock voltage Horizontal shift register clock voltage Summing gate voltage Reset gate voltage Transfer gate voltage High Low High Low High Low High Low High Low s Electrical and optical characteristics (Ta=25 C) Parameter Symbol Saturation output voltage Vsat Full well capacity * 1 FW CCD node sensitivity Sv Dark current * 1, * 2 DS Readout noise* 3 Nr Dynamic range DR Photo response non-uniformity * 4 PRNU Spectral response range *1: TDI mode *2: Line rate 50 kHz, accumulated dark signal after 128-stage transfer *3: Readout frequency 30 MHz *4: Measured at one-half of the full well. In TDI mode. Min. 100 3 Typ. FW x Sv 120 3.5 100 100 1200 3 200 to 1100 Max. 140 4 300 200 10 Unit V ke V/e e -/pixel e - rms % nm s Electrical characteristics (Ta=25 C) Min. S10200-02 Vertical shift register S10201-04 CP1V, CP2V, CP3V capacitance S10202-08/-16 S10200-02 S10201-04 Line rate LR S10202-08 S10202-16 S10200-02 Horizontal shift register S10201-04 CP1H, CP2H capacitance S10202-08/-16 S10200-02 Transfer gate capacitance S10201-04 CTG S10202-08/-16 S10200-02 Summing gate capacitance S10201-04 CSG S10202-08/-16 S10200-02 Reset gate capacitance S10201-04 CRG S10202-08/-16 Charge transfer efficiency * 5 CTE 0.99995 Output level * 6 Vout Output impedance * 7 Zo Output MOSFET supply current/node Ido Power consumption * 6, * 7 P *5: Charge transfer efficiency per pixel, measured at half of the full well capacity. *6: VOD=15 V, Load resistance=2.2 k *7: Power consumption of the on-chip amplifier plus load resistance. Parameter Signal output frequency Reset clock frequency Symbol fc frg Typ. 30 30 250 400 650 50 50 50 100 50 90 90 40 60 100 20 40 40 20 40 40 0.99999 6.5 300 5 75 Max. 40 40 10 Unit MHz MHz pF kHz pF pF pF pF V mA mW 4 Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 s Device structure (Typical example: S10202-08) Conceptual drawing of top view THINNING OSb1 OSb2 OSb3 OSb6 OSb7 OSb8 OSa1 OSa2 OSa3 OSa6 OSa7 8 BLANK 512 PIXELS OSa8 V=128 H=512 x 8 (Number of ports) 128 TDI STAGE KMPDC0252EA s Timing chart B port side readout OSb S510 S254 S511 S255 S512 : S10200-02, S10201-04, S10202-08 S256 : S10202-16 D1 D2 D3..D8, S1..S509 D3..D8, S1..S253 THINNING Tprr, Tpwr, Tpfr RGb Tprs, Tpws, Tpfs P2Hb, SGb Tovr S10200-02, S10201-04, S10202-08: 518 S10202-16: 262 P1Hb 519 263 520 264 Tprv, Tpwv, Tpfv TGb P1V P2V P3V TGa P1Ha P2Ha, SGa RGa OSa KMPDC0253EB Tprh, Tpwh, Tpfh 1 2 4..517 3 4..261 Tovrv 5 Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 A port side readout OSb RGb P2Hb, SGb P1Hb TGb P1V P2V P3V TGa 518 262 P1Ha P2Ha, SGa RGa OSa S510 S254 S511 S255 S512 : S10200-02, S10201-04, S10202-08 S256 : S10202-16 D1 D2 D3..D8, S1..S509 D3..D8, S1..S253 KMPDC0254EB 519 263 520 : S10200-02, S10201-04, S10202-08 264 : S10202-16 1 2 3 4..517 4..261 Parameter Symbol Min. Pulse width Tpwv 120 P1V, 2V, 3V, TG Rise and fall time Tprv, Tpfv 2 Overlap time Tovrv 30 Pulse width *8 Tpwh 12.5 P1H, P2H Rise and fall time *8 Tprh, Tpfh 3 Duty ratio *8 Pulse width Tpws 12.5 SG Rise and fall time Tprs, Tpfs 2 Duty ratio Pulse width Tpwr 5 RG Rise and fall time Tprr, Tpfr 1 TG - P1H Overlap time Tovr 30 *8: Symmetrical clock pulses should be overlapped at 50 % of maximum pulse amplitude. Typ. 770 10 300 16.5 6 50 16.5 4 50 6 2 1000 Max. - Unit ns ns ns ns ns % ns ns % ns ns ns s Dimensional outlines (unit: mm) S10200-02 ACTIVE AREA 1.536 30.48 0.35 27.94 0.33 ACTIVE AREA 12.288 40 21 3.3 0.25 2.5 0.1 INDEX MARK 1.48 0.15 * 0.457 0.05 3 0.1 1.27 0.1 * Distance between window surface and photosensitive surface 0.25 -0.03 +0.05 1 20 10.16 0.25 9.91 0.25 KMPDA0218EA 6 Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 S10201-04 ACTIVE AREA 1.536 40.64 0.45 38.1 0.43 ACTIVE AREA 24.576 40 21 3.3 0.25 2.5 0.1 INDEX MARK 1.48 0.15 * 3 0.1 0.457 0.05 1.27 0.1 * Distance between window surface and photosensitive surface KMPDA0219EA S10202-08/-16 ACTIVE AREA 1.536 66.04 0.66 63.5 0.64 55 0.1 ACTIVE AREA 49.152 100 51 3.5 0.35 2.2 0.22 0.8 0.05 2.5 0.25 0.25 -0.03 +0.05 1 20 10.16 0.25 9.91 0.25 0.25 -0.03 10.16 0.25 9.91 0.25 6.5 0.1 1 INDEX MARK 50 2.18 0.2 * 3 0.3 1.27 0.13 0.46 0.25 * Distance between window surface and photosensitive surface KMPDA0220EA +0.05 7 Back-thinned TDI-CCD s Pin connections S10200-02, S10201-04, S10202-08, S10202-16 S10201-04 Function CCD vertical register clock-2 CCD vertical register clock-3 CCD vertical register clock-1 Transfer gate-a Digital GND Analog GND Output transistor source-a1 Output transistor source-a2 Output transistor source-a3 Output transistor source-a4 Analog GND Output drain Reset drain Output gate Overflow drain Digital GND Reset gate-a Summing gate-a CCD horizontal register-a clock-2 CCD horizontal register-a clock-2 CCD horizontal register-b clock-2 CCD horizontal register-b clock-1 Summing gate-b Reset gate-b Digital GND Overflow gate Output gate Reset drain Output drain Analog GND Output transistor source-b4 Output transistor source-b3 Output transistor source-b2 Output transistor source-b1 Analog GND Digital GND Transfer gate-b CCD vertical register clock-1 CCD vertical register clock-3 CCD vertical register clock-2 S10200-02 Pin No. Symbol Function CCD vertical register clock-2 1 P2V CCD vertical register clock-3 2 P3V CCD vertical register clock-1 3 P1V 4 TGa Transfer gate-a 5 DGND Digital GND 6 AGND Analog GND 7 8 OSa1 Output transistor source-a 1 9 OSa2 Output transistor source-a 2 10 11 AGND Analog GND Output drain 12 OD Reset drain 13 RD Output gate 14 OG 15 OFD Overflow drain 16 DGND Digital GND 17 RGa Reset gate-a 18 SGa Summing gate-a CCD horizontal register-a 19 P1Ha clock-2 CCD horizontal register-a 20 P2Ha clock-2 CCD horizontal register-b 21 P2Hb clock-2 CCD horizontal register-b 22 P1Hb clock-1 23 SGb Summing gate-b 24 RGb Reset gate-b 25 DGND Digital GND 26 OFG Overflow gate Output gate 27 OG Reset drain 28 RD Output drain 29 OD 30 AGND Analog GND 31 32 OSb2 Output transistor source-b2 33 OSb1 Output transistor source-b1 34 35 AGND Analog GND 36 DGND Digital GND 37 TGb Transfer gate-b CCD vertical register clock-1 38 P1V CCD vertical register clock-3 39 P3V CCD vertical register clock-2 40 P2V Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol P2V P3V P1V TGa DGND AGND OSa1 OSa2 OSa3 OSa4 AGND OD RD OG OFD DGND RGa SGa P1Ha P2Ha P2Hb P1Hb SGb RGb DGND OFG OG RD OD AGND OSb4 OSb3 OSb2 OSb1 AGND DGND TGb P1V P3V P2V 8 Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 S10202-08 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol P2V P3V P1V TGa DGND OFG OFD RD OD AGND OSa1 OSa2 OSa3 OSa4 AGND OG DGND RGa1 SGa1 P1Ha1 P2Ha1 P2Ha2 P1Ha2 DGND AGND OSa5 OSa6 OSa7 OSa8 AGND OD RD OG OFD OFG DGND RGa2 SGa2 TGa P1V P3V P2V Function CCD vertical register clock-2 CCD vertical register clock-3 CCD vertical register clock-1 Transfer gate-a Digital GND Overflow gate Overflow drain Reset drain Output drain Analog GND Output transistor source-a1 Output transistor source-a2 Output transistor source-a3 Output transistor source-a4 Analog GND Output gate Digital GND Reset gate-a 1 Summing gate-a 1 CCD horizontal register-a1 clock-2 CCD horizontal register-a1 clock-2 CCD horizontal register-a2 clock-2 CCD horizontal register-a2 clock-1 Digital GND Analog GND Output transistor source-a5 Output transistor source-a6 Output transistor source-a7 Output transistor source-a8 Analog GND Output drain Reset drain Output gate Overflow drain Overflow gate Digital GND Reset gate-a 2 Summing gate-a 2 Transfer gate-a CCD vertical register clock-1 CCD vertical register clock-3 CCD vertical register clock-2 Symbol P2V P3V P1V TGb SGb2 RGb2 DGND OFG OFD OG RD OD AGND OSb8 OSb7 OSb6 OSb5 AGND DGND P1Hb2 P2Hb2 P2Hb1 P1Hb1 SGb1 RGb1 DGND OG AGND OSb4 OSb3 OSb2 OSb1 AGND OD RD OFD OFG DGND TGb P1V P3V P2V Function CCD vertical register clock-2 CCD vertical register clock-3 CCD vertical register clock-1 Transfer gate-b Summing gate-b 2 Reset gate-b 2 Digital GND Overflow gate Overflow drain Output gate Reset drain Output drain Analog GND Output transistor source-b8 Output transistor source-b7 Output transistor source-b6 Output transistor source-b5 Analog GND Digital GND CCD horizontal register-b2 clock-2 CCD horizontal register-b2 clock-2 CCD horizontal register-b1 clock-2 CCD horizontal register-b1 clock-2 Summing gate-b 1 Reset gate-b 1 Digital GND Output gate Analog GND Output transistor source-b4 Output transistor source-b3 Output transistor source-b2 Output transistor source-b1 Analog GND Output drain Reset drain Overflow drain Overflow gate Digital GND Transfer gate-b CCD vertical register clock-1 CCD vertical register clock-3 CCD vertical register clock-2 9 Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 S10202-16 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol P2V P3V P1V TGa DGND OFG OFD RD OD AGND OSa1 OSa2 OSa3 OSa4 OSa5 OSa6 OSa7 OSa8 AGND OG DGND RGa1 SGa1 P1Ha1 P2Ha1 P2Ha2 P1Ha2 DGND AGND OSa9 OSa10 OSa11 OSa12 OSa13 OSa14 OSa15 OSa16 AGND OD RD OG OFD OFG DGND RGa2 SGa2 TGa P1V P3V P2V Function CCD vertical register clock-2 CCD vertical register clock-3 CCD vertical register clock-1 Transfer gate-a Digital GND Overflow gate Overflow drain Reset drain Output drain Analog GND Output transistor source-a1 Output transistor source-a2 Output transistor source-a3 Output transistor source-a4 Output transistor source-a5 Output transistor source-a6 Output transistor source-a7 Output transistor source-a8 Analog GND Output gate Digital GND Reset gate-a 1 Summing gate-a 1 CCD horizontal register-a1 clock-2 CCD horizontal register-a1 clock-2 CCD horizontal register-a2 clock-2 CCD horizontal register-a2 clock-1 Digital GND Analog GND Output transistor source-a9 Output transistor source-a10 Output transistor source-a11 Output transistor source-a12 Output transistor source-a13 Output transistor source-a14 Output transistor source-a15 Output transistor source-a16 Analog GND Output drain Reset drain Output gate Overflow drain Overflow gate Digital GND Reset gate-a 2 Summing gate-a 2 Transfer gate-a CCD vertical register clock-1 CCD vertical register clock-3 CCD vertical register clock-2 Symbol P2V P3V P1V TGb SGb2 RGb2 DGND OFG OFD OG RD OD AGND OSb16 OSb15 OSb14 OSb13 OSb12 OSb11 OSb10 OSb9 AGND DGND P1Hb2 P2Hb2 P2Hb1 P1Hb1 SGb1 RGb1 DGND OG AGND OSb8 OSb7 OSb6 OSb5 OSb4 OSb3 OSb2 OSb1 AGND OD RD OFD OFG DGND TGb P1V P3V P2V Function CCD vertical register clock-2 CCD vertical register clock-3 CCD vertical register clock-1 Transfer gate-b Summing gate-b 2 Reset gate-b 2 Digital GND Overflow gate Overflow drain Output gate Reset drain Output drain Analog GND Output transistor source-b16 Output transistor source-b15 Output transistor source-b14 Output transistor source-b13 Output transistor source-b12 Output transistor source-b11 Output transistor source-b10 Output transistor source-b9 Analog GND Digital GND CCD horizontal register-b2 clock-2 CCD horizontal register-b2 clock-2 CCD horizontal register-b1 clock-2 CCD horizontal register-b1 clock-2 Summing gate-b 1 Reset gate-b 1 Digital GND Output gate Analog GND Output transistor source-b8 Output transistor source-b7 Output transistor source-b6 Output transistor source-b5 Output transistor source-b4 Output transistor source-b3 Output transistor source-b2 Output transistor source-b1 Analog GND Output drain Reset drain Overflow drain Overflow gate Digital GND Transfer gate-b CCD vertical register clock-1 CCD vertical register clock-3 CCD vertical register clock-2 10 Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 s Precaution for use (Electrostatic countermeasures) q Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an earth ring, in order to prevent electrostatic damage due to electrical charges from friction. q Avoid directly placing these sensors on a work-desk, etc. that may carry an electrostatic charge. q Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to discharge. q Ground the tools used to handle these sensors, such as tweezers and soldering irons. It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the amount of damage that occurs. TDI camera C10000 series The TDI camera C10000 series is useful in a wide range of imaging applications that require both high speed and high sensitivity, including in-line monitoring and inspection. s Specifications C10000-301 C10000-401 1024 (H) x 128 (V) 2048 (H) x 128 (V) Back-thinned type 12 m (H) x 12 m (V) 12.29 mm (H) x 1.536 mm (V) 24.58 mm (H) x 1.536 mm (V) Bi direction TDI readout mode or Frame readout mode *9 2 ports (512 x 2) 4 ports (512 x 4) Lateral overflow drain (x 100) 30 MHz 0.45 kHz to 50 kHz 100000 electrons 130 electrons rms 770 : 1 12-bit / 8-bit *10 Real-time shading correction with internal DSP C-mount F-mount Base configuration 60 MHz 1 port (1024 x 1) 2 ports (1024 x 2) Internal setting by serial command *11 TDI line rate control External trigger Analog enhancement gain 0 dB to 14 dB Power / DC +12 V / 20 V * A Power consumption Camera control Serial control in Camera link *9: Frame readout mode is useful for easy focusing, but it is not suitable for measurement. Please consult with our sales office for details. *10: Selectable by serial command. *11: Internal TDI line rate can be set in 33 ns steps. Parameter Pixel number Device structure Pixel size Effective area TDI transfer direction Readout mode TDI output channel Anti-blooming TDI pixel clock rate TDI line rate Full-well capacity (Typ.) Readout noise (Typ.) Dynamic range (Typ.) A/D converter Image processing Lens mount Interface Camera output clock Camera output channel Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. (c)2007 Hamamatsu Photonics K.K. HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, www.hamamatsu.com U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvagen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Cat. No. KMPD1098E02 Apr. 2007 DN 11 |
Price & Availability of S10202-16
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